ARM11 Performance Counter Event List

The ARM11 cores used in iOS devices contain three independent performance counters. The first counter can count only cycle counts, while the other two (which are identical) can count 25 different types of events.

The table below lists each Event Name, the counter (PMC) number(s) for counters which can count the event, and each event’s number.

For more information on how to configure these counters, see ARM11 CPU Performance Counter Configuration.

Performance Counter Event Name

PMC Number(s)

Event Number

Branch instruction executed

2-3

5

Branch mispredicted

2-3

6

Cycle Count

1,2-3

0,255

Data cache access, no cache operations (cacheable accesses only)

2-3

9

Data cache access, no cache operations

2-3

10

Data cache miss, no cache operations

2-3

11

Data cache writeback per 4 words

2-3

12

Data MicroTLB miss

2-3

4

ETMEXTOUT[0,1] asserts

2-3

34

ETMEXTOUT[0] asserts

2-3

32

ETMEXTOUT[1] asserts

2-3

33

Explicit external data access

2-3

16

Instruction cache miss requires fetch

2-3

0

Instruction executed

2-3

7

Instruction MicroTLB miss

2-3

3

Main TLB miss

2-3

15

Procedure call instruction executed

2-3

35

Procedure return instruction executed, return address predicted incorrectly

2-3

38

Procedure return instruction executed, return address predicted

2-3

37

Procedure return instruction executed

2-3

36

Software changed the PC

2-3

13

Stall, data dependency

2-3

2

Stall, instruction buffer cannot deliver

2-3

1

Stall, LSU request queue full

2-3

17

Write buffer drained count

2-3

18



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